1. Field of the Invention
The present invention relates to memory devices, in particular, including nonvolatile and volatile memories.
2. Description of the Related Art
FIG. 9 is a block diagram showing the construction of a conventional memory device. A microcontroller 901 is connected to a nonvolatile memory (NV memory) 905 through a bus and to a RAM 906, an error correction circuit 903, and a nonvolatile memory 902 through another bus. The nonvolatile memory 902 is a NOR flash memory, and the nonvolatile memory 905 is a NAND flash memory.
The NOR flash memory 902 can be random-accessed. For this reason, the microcontroller 901 can directly access the NOR flash memory 902 through the bus. However, the NOR flash memory 902 is disadvantageous because of its small capacity, large size, and high power consumption.
To cope with these problems, the NAND flash memory 905 having advantages such as a large capacity, small size, and low power consumption is added to the memory device. However, the NAND flash memory 905 can only be sequentially accessed and therefore requires the RAM 906 to enable a random access. That is, the microcontroller 901 sequentially transfers data from the NAND flash memory 905 to the RAM 906, and thereafter random access to the RAM 906 is possible.
Although the NAND flash memory 905 has the above advantages, it requires the error detection and correction circuit 903 because data reliability is low. The error detection and correction method will be described next.
FIG. 10 is a block diagram showing the error detection and correction method in the memory device shown in FIG. 9. The microcontroller 901 includes a buffer 1001.
A method for the microcontroller 901 transferring data from the RAM 906 to the NAND flash memory 905 will be described. First, the microcontroller 901 reads out actual data (512 bytes) 1014 from the RAM 906 to the buffer 1001 and supplies actual data 1012 to the error detection and correction circuit (EGC) 903. The error detection and correction circuit 903 generates error detection and correction data (3 bytes) 1013 on the basis of the actual data (512 bytes) 1012. The microcontroller 901 reads out the error detection and correction data 1013 to the buffer 1001 and writes the actual data and error detection and correction data (512+3 bytes) 1011 in the NAND flash memory 905.
The NAND flash memory 905 has a storage area of a plurality of pages. Each page has an actual data area and a spare data area. The actual data is stored in the actual data area, and the error detection and correction data is stored in the spare data area.
A method for the microcontroller 901 transferring data from the NAND flash memory 905 to the RAM 906 will be described next. The microcontroller 901 reads out the actual data and error detection and correction data (512+3 bytes) 1011 from the NAND flash memory 905 to the buffer 1001. Next, the microcontroller 901 supplies the actual data (512 bytes) 1012 in the buffer 1001 to the error detection and correction circuit 903. The error detection and correction circuit 903 generates the error detection and correction data (3 bytes) 1013 on the basis of the actual data 1012. The microcontroller 901 reads out the error detection and correction data 1013 and checks whether or not the error detection and correction data 1013 is the same as the error detection and correction data previously read out from the NAND flash memory 905. When the two data are the same, it means that the actual data in the buffer 1001 has no error. When the two data are not the same, it means that the actual data in the buffer 1001 has an error.
If the actual data has no error, the microcontroller 901 writes the actual data 1014 in the buffer 1001 into the RAM 906 without any change. If the actual data has an error, the microcontroller 901 specifies the error bit in accordance with the check result, corrects the actual data in the buffer 1001, and writes the corrected actual data 1014 into the RAM 906.
FIG. 11 is a representation of a NAND flash memory 1101 and the RAM 1111 for illustrating the concept of the above error detection and correction method. The NAND flash memory 1101 includes pages 1102, 1103, 1104, and so on. Each of the pages 1102 to 1104 has an actual data area and spare data area. The actual data area is for storing actual data, and the spare data area is for storing spare data (including error detection and correction data). Each page is for actual data of, e.g., 512 bytes and error detection and correction data of, e.g., 3 bytes.
Data transfer from the RAM 1111 to the NAND flash memory 1101 will be described first. The RAM 1111 stores actual data 1112. A microcontroller 1121 makes the actual data 1112 (e.g., 512 bytes) in the RAM 1111 one-to-one-correspond to spare data 1122 (e.g., 3 bytes) in the internal buffer of the microcontroller 1121 and writes actual data 1152 and spare data 1151 in the NAND flash memory 1101.
Data transfer from the NAND flash memory 1101 to the RAM 1111 will be described next. The NAND flash memory 1101 stores actual data and spare data. The microcontroller 1121 reads out actual data 1141 and spare data 1142 from the NAND flash memory 1101. Only the actual data 1141 is written in the RAM 1111 as the actual data 1112, and the spare data 1142 is deleted as delete data 1131 without being stored in the RAM 1111.
The spare data stored in the NAND flash memory 1101 contains not only the above error detection and correction data but also management information and control information. Hence, to correct the actual data, the spare data must be corrected accordingly.
To correct actual data on the RAM 1111 and write the data in the NAND flash memory 1101, the microcontroller 1121 temporarily reads out spare data from the NAND flash memory 1101 and corrects the spare data. Then, the microcontroller 1121 writes the corrected spare data and the corrected actual data on the RAM 1111 in the NAND flash memory 1101. As described above, to correct spare data, the data must be temporarily read out from the NAND flash memory 1101. For this reason, the number of processing steps is large, and the processing speed is low.
As described above, in the memory device including the NAND flash memory 905, data transfer between the NAND flash memory 905 and the RAM 906 is necessarily performed. During this data transfer, the bus connecting the microcontroller 901 with the RAM 906 is occupied, as shown in FIG. 9, so the microcontroller 901 cannot access the NOR flash memory 902.
Besides, as shown in FIG. 10, upon data transfer between the NAND flash memory 905 and the RAM 906, at least four data transfer processes 1011 to 1014 must be executed. This means that the data transfer requires a long time.
Besides, the buffer 1001 in the microcontroller 901 requires a memory capacity of at least 512+3 bytes to read/write actual data (512 bytes) and error detection and correction data (3 bytes) from/in the NAND flash memory 905.
Besides, since the NAND flash memory 905 and the RAM 906 have different electrical specifications, the microcontroller 901 must control the NAND flash memory 905 and the RAM 906 using power supply voltages corresponding to the respective electrical specifications. For this reason, the microcontroller 901 can not use its original low power supply voltage, and so low power consumption cannot be realized.
As shown in FIG. 11, to correct spare data in the NAND flash memory 1101, the spare data must be temporarily read out from the NAND flash memory 1101. For this reason, the number of processing steps is large, and the processing speed is low.